EPA ECC: Error-Pattern-Aligned ECC for HBM2E

Abstract

DRAM vendors introduced On-Die Error Correction Codes (OD-ECC) to correct errors internally. Most OD-ECCs are based on Single Error Correction to correct individual bit errors. However, recent soft error experiments on HBM2 reveal that DRAM frequently experiences multi-bit errors, necessitating a stronger OD-ECC solution. This paper introduces a novel OD-ECC, EPA ECC, specifically designed to correct frequently-observed multi-bit error patterns. The key innovation of EPA ECC is the construction of multi-bit symbols aligned with common error patterns, and the application of Reed-Solomon codes to correct severe errors without increasing the redundancy ratio. Our evaluation demonstrates that EPA ECC provides higher memory reliability than the current SEC-DED OD-ECC without incurring significant system performance degradation. © 2023 IEEE.