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A 12.5-Gb/s Near-Ground Transceiver Employing a MaxEye Algorithm-Based Adaptation Technique
- Authors
- Jin, J[Jin, Jahoon]; Kim, S[Kim, Seok]; Jin, X[Jin, Xuefan]; Kim, SH[Kim, Sang-Hoon]; Chun, JH[Chun, Jung-Hoon]
- Issue Date
- Mar-2018
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- AC-coupled equalization (EQ); adaptive equalization; dual-loop clock and data recovery (CDR); finite-impulse response (FIR); high-speed interface; intersymbol interference (ISI); near ground; timing margin; transceiver; voltage mode
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.26, no.3, pp.522 - 530
- Indexed
- SCIE
SCOPUS
- Volume
- 26
- Number
- 3
- Start Page
- 522
- End Page
- 530
- ISSN
- 1063-8210
- Abstract
- A 12.5-Gb/s complete near-ground transceiver is demonstrated. The output stage of the transmitter (TX) employs 2-tap finite-impulse response equalization (EQ) and also performs ac-coupled EQ for an additional EQ. A continuous-time linear equalizer (CTLE) on the receiver (RX) side compensates for the channel attenuation. Based on the maximum eye algorithm, the peaking gain of CTLE is adaptively controlled to track a time-variant environment, such as PVT variations. Each TX and RX is implemented with clocking circuits: a differential PLL, and a dual-loop clock and data recovery circuit. The proposed transceiver is fabricated in a 45-nm CMOS process, and the entire TX and RX, respectively, consume 92 and 138 mW under a 1.2-V supply while operating at 12.5 Gb/s.
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Related Researcher
- CHUN, JUNG HOON
- Information and Communication Engineering (Semiconductor Systems Engineering)