Power-Supply Rejection Model Analysis of Capacitor-Less LDO Regulator Designs
- Authors
- Joo, S[Joo, Soyeon]; Kim, J[Kim, Jintae]; Kim, S[Kim, SoYoung]
- Issue Date
- May-2017
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- power-supply rejection (PSR); low drop-out (LDO) regulator; pass transistor; two-stage op-amp
- Citation
- IEICE TRANSACTIONS ON ELECTRONICS, v.E100C, no.5, pp.504 - 512
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEICE TRANSACTIONS ON ELECTRONICS
- Volume
- E100C
- Number
- 5
- Start Page
- 504
- End Page
- 512
- URI
- https://scholarworks.bwise.kr/skku/handle/2021.sw.skku/29274
- DOI
- 10.1587/transele.E100.C.504
- ISSN
- 1745-1353
- Abstract
- This paper presents accurate DC and high frequency power-supply rejection (PSR) models for low drop-out (LDO) regulators using different types of active loads and pass transistors. Based on the proposed PSR model, we suggest design guidelines to achieve a high DC PSR or flat bandwidth (BW) by choosing appropriate active loads and pass transistors. Our PSR model captures the intricate interaction between the error amplifiers (EAs) and the pass devices by redefining the transfer function of the LDO topologies. The accuracy of our model has been verified through SPICE simulation and measurements. Moreover, the measurement results of the LDOs fabricated using the 0.18 mu m CMOS process are consistent with the design guidelines suggested in this work.
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- Appears in
Collections - Information and Communication Engineering > Department of Semiconductor Systems Engineering > 1. Journal Articles
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