Detailed Information
Cited 1 time in 
Cited 0 time in 
Cited 0 time in
Metadata Downloads
Bulk-FinFETs implementing insulating layer under source and drain for DRAM cell application
- Authors
- Park, JS[Park, J. -S.]; Park, JM[Park, J. -M.]; Han, SY[Han, S. -Y.]; Yamada, S[Yamada, S.]; Roh, YH[Roh, Y. -H.]; Park, DG[Park, D. -G.]
- Issue Date
- 19-Jun-2008
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Citation
- ELECTRONICS LETTERS, v.44, no.13, pp.824 - U61
- Indexed
- SCIE
SCOPUS
- Journal Title
- ELECTRONICS LETTERS
- Volume
- 44
- Number
- 13
- Start Page
- 824
- End Page
- U61
- ISSN
- 0013-5194
- Abstract
- Partially-insulated oxide (PIOX) layers are implemented under the source/drain region in bulk FinFETs. The improved short channel effect by controlling the sub-channel on the bottom part of the gate in bulk FinFETs, the decreased junction leakage current due to blocking the vertical leakage path by PIOX layers, and the increased hot carrier lifetime can be applicable to future DRAM cell transistors.
- Files in This Item
- There are no files associated with this item.
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.