Electrical stabilities of half-Corbino thin-film transistors with different gate geometries
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jung, H. | - |
dc.contributor.author | Choi, K.-Y. | - |
dc.contributor.author | Lee, H. | - |
dc.date.available | 2018-05-10T07:49:58Z | - |
dc.date.created | 2018-04-17 | - |
dc.date.issued | 2012 | - |
dc.identifier.issn | 1598-0316 | - |
dc.identifier.uri | http://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/13297 | - |
dc.description.abstract | In this study, the bias-temperature stress and current-temperature stress induced by the electrical stabilities of half-Corbino hydrogenated-amorphous-silicon (a-Si:H) thin-film transistors (TFTs) with different gate electrode geometries fabricated on the same substrate were examined. The influence of the gate pattern on the threshold voltage shift of the half-Corbino a-Si:H TFTs is discussed in this paper. The results indicate that the half-Corbino a-Si:H TFT with a patterned gate electrode has enhanced power efficiency and improved aperture ratio when compared with the half-Corbino a-Si:H TFT with an unpatterned gate electrode and the same source/drain electrode geometry. © 2012 Copyright The Korean Information Display Society. | - |
dc.relation.isPartOf | Journal of Information Display | - |
dc.subject | a-Si:H | - |
dc.subject | A-Si:H TFT | - |
dc.subject | Aperture ratio | - |
dc.subject | Bias-temperature stress | - |
dc.subject | Electrical stability | - |
dc.subject | Gate electrodes | - |
dc.subject | Gate geometry | - |
dc.subject | Gate patterns | - |
dc.subject | half-Corbino | - |
dc.subject | Power efficiency | - |
dc.subject | Source/drain electrodes | - |
dc.subject | Stress-induced | - |
dc.subject | Thin-film transistor (TFTs) | - |
dc.subject | Threshold voltage shifts | - |
dc.subject | Semiconducting organic compounds | - |
dc.subject | Silicon | - |
dc.subject | Thin film transistors | - |
dc.subject | Amorphous silicon | - |
dc.title | Electrical stabilities of half-Corbino thin-film transistors with different gate geometries | - |
dc.type | Article | - |
dc.identifier.doi | 10.1080/15980316.2011.652197 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | Journal of Information Display, v.13, no.1, pp.51 - 54 | - |
dc.identifier.kciid | ART001643755 | - |
dc.description.journalClass | 1 | - |
dc.identifier.scopusid | 2-s2.0-84861010651 | - |
dc.citation.endPage | 54 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 51 | - |
dc.citation.title | Journal of Information Display | - |
dc.citation.volume | 13 | - |
dc.contributor.affiliatedAuthor | Lee, H. | - |
dc.type.docType | Article | - |
dc.description.oadoiVersion | published | - |
dc.subject.keywordAuthor | bias-temperature stress | - |
dc.subject.keywordAuthor | current-temperature stress | - |
dc.subject.keywordAuthor | gate geometry | - |
dc.subject.keywordAuthor | half-Corbino | - |
dc.subject.keywordAuthor | thin-film transistor | - |
dc.description.journalRegisteredClass | scopus | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
Soongsil University Library 369 Sangdo-Ro, Dongjak-Gu, Seoul, Korea (06978)02-820-0733
COPYRIGHT ⓒ SOONGSIL UNIVERSITY, ALL RIGHTS RESERVED.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.