Electrical stabilities of half-Corbino thin-film transistors with different gate geometries
- Authors
- Jung, H.; Choi, K.-Y.; Lee, H.
- Issue Date
- 2012
- Keywords
- bias-temperature stress; current-temperature stress; gate geometry; half-Corbino; thin-film transistor
- Citation
- Journal of Information Display, v.13, no.1, pp.51 - 54
- Journal Title
- Journal of Information Display
- Volume
- 13
- Number
- 1
- Start Page
- 51
- End Page
- 54
- URI
- http://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/13297
- DOI
- 10.1080/15980316.2011.652197
- ISSN
- 1598-0316
- Abstract
- In this study, the bias-temperature stress and current-temperature stress induced by the electrical stabilities of half-Corbino hydrogenated-amorphous-silicon (a-Si:H) thin-film transistors (TFTs) with different gate electrode geometries fabricated on the same substrate were examined. The influence of the gate pattern on the threshold voltage shift of the half-Corbino a-Si:H TFTs is discussed in this paper. The results indicate that the half-Corbino a-Si:H TFT with a patterned gate electrode has enhanced power efficiency and improved aperture ratio when compared with the half-Corbino a-Si:H TFT with an unpatterned gate electrode and the same source/drain electrode geometry. © 2012 Copyright The Korean Information Display Society.
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