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A Novel Clock Distribution Technique for Asynchronous Pipelined-SFQ Sequential Logic using Variable Delay-controlled JTLs

Authors
위재경
Issue Date
Oct-2005
Citation
International Superconductive Electronics Conference, pp.449 - 455
URI
http://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/30265
Conference Name
International Superconductive Electronics Conference
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