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HYFII: HYbrid Fault Injection Infrastructure for Accurate Runtime System Failure Analysis

Authors
Jang, SungminPark, Jaeyoung
Issue Date
Aug-2020
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
Circuit faults; Integrated circuit modeling; Logic gates; Analytical models; Runtime; Computational modeling; Timing; Circuit analysis; circuit faults; electrical fault detection; failure analysis; table lookup
Citation
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.28, no.8, pp.1893 - 1900
Journal Title
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume
28
Number
8
Start Page
1893
End Page
1900
URI
http://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/39905
DOI
10.1109/TVLSI.2020.2992982
ISSN
1063-8210
Abstract
In this article, we propose an efficient circuit reliability analysis infrastructure utilizing on-demand transistor-accurate fault injection based on workload-specific distributional properties. A novel two-phase approach is developed to achieve circuit-level accuracy, via careful transistor-level precharacterization, and gate-level efficiency, via fast runtime fault generation. A time-consuming circuit characterization is performed once, and the result of the precharacterization is used multiple times at runtime to inject faults. Also, novel fault probability estimation and fault injection methods are developed. Fault probabilities are computed based on workload-specific voltage/temperature distribution, and faults are injected efficiently by scaling the computed fault probabilities. We demonstrate the proposed methodology on an OpenSPARC core targeting an implementation on a 32-nm technology node. Analysis indicates that the injector computes the system failure rate with 0.1-ms simulation overhead per injection while having circuit-level accuracy.
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