Design of a K-Band High-Linearity Asymmetric SPDT CMOS Switch Using a Stacked Transistor

Abstract

This study presents a high-linearity K-band single-pole double-throw (SPDT) switch with asymmetric topology in a 65-nm CMOS process for 5G applications. To simultaneously obtain high power-handling capability and high isolation in the Tx and Rx modes, respectively, we propose an SPDT switch using asymmetric topology and the stacked-transistor technique. In both the Tx/Rx modes, the proposed SPDT switch operates with an insertion loss of less than 2.1 dB and isolation better than 22.5 dB in the frequency range 20-25 GHz. At 22 GHz, the measurement results of the input 1-dB compression point (IP1dB) are 32.5 and 4.7 dBm in Tx and Rx modes, respectively. The chip core size of the proposed SPDT switch is 0.03 mm(2).