Ka-Band CMOS x5 Frequency Multiplier With Current-Reuse Technique
- Authors
- Lim, Jeong-Taek; Choi, Han-Woong; Song, Jae-Hyeok; Choi, Sunkyu; Park, Changkun; Kim, Choul-Young
- Issue Date
- Aug-2023
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- CMOS; frequency multiplier; frequency quintupler; Ka-band; low power
- Citation
- IEEE MICROWAVE AND WIRELESS TECHNOLOGY LETTERS, v.33, no.8, pp.1227 - 1230
- Journal Title
- IEEE MICROWAVE AND WIRELESS TECHNOLOGY LETTERS
- Volume
- 33
- Number
- 8
- Start Page
- 1227
- End Page
- 1230
- URI
- https://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/44605
- DOI
- 10.1109/LMWT.2023.3276412
- ISSN
- 2771-957X
- Abstract
- In this study, we propose a Ka-band x5 frequency multiplier implemented through a 65-nm CMOS process. The frequency quintupler core is merged with the common-source (CS) amplifier in a current-reuse structure to achieve low power consumption. To further improve harmonic suppression, the interstage matching network of the frequency quintupler core is constructed using a third-order high-pass filter (HPF). The proposed quintupler core was implemented as a high conversion gain x5 frequency multiplier along with input/output buffer and notch filter. The size of the proposed x5 frequency multiplier was 0.81 x 0.95 mm, including the input and output buffers. Furthermore, the measurement results of the x5 frequency multiplier showed that the conversion gain for the 27.3-28.6 GHz range was 30.7-31.3 dB at input power values of -34 dBm, and the harmonic suppression is in the 30.9-37.5 dBc. In the operating frequency band, the input and output return losses are greater than 10 dB, and the power consumption was 23 mW.
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