A Capacitorless External-Clock-Free Fully Synthesizable Digital LDO With Time-Based Load-State Decision and Asynchronous Recovery
- Authors
- Oh, Jonghyun; Song, Yoonho; Hwang, Young-Ha; Park, Jun-Eun; Seok, Mingoo; Jeong, Deog-Kyoon
- Issue Date
- Jan-2024
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- Asynchronous; capacitor-free; clock-free; digital low-dropout regulator (DLDO); low-dropout regulator (LDO); power management; synthesizable; time-based
- Citation
- IEEE Transactions on Power Electronics, v.39, no.1, pp 985 - 997
- Pages
- 13
- Journal Title
- IEEE Transactions on Power Electronics
- Volume
- 39
- Number
- 1
- Start Page
- 985
- End Page
- 997
- URI
- https://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/49265
- DOI
- 10.1109/TPEL.2023.3321052
- ISSN
- 0885-8993
1941-0107
- Abstract
- This article presents an external-clock-free fully synthesizable digital low-dropout regulator (DLDO) without an output capacitor. To lower quiescent current in a steady state, time-based load-state decision is exploited to change an internal clock frequency depending on a load state, while employing a single comparator, a single reference voltage, and a single delay line. In addition, for small voltage droop and short settling time without an output-load capacitor, a asynchronous response to voltage droop and a fast-recovery technique are exploited using a load-direct droop detector and a coarse controller. Besides, in order to obtain full synthesizability, all circuits including pass gates are made up of industry-standard cells and all blocks are implemented using a commercial script-based auto place-and-route tool. The DLDO prototype fabricated in a 40-nm CMOS process occupies a total area of 0.0035 mm$^{2}$. When load current is changed from 0.78 to 39.2 mA with 2.2-ns edge time, voltage droop and settling time are measured as 98 mV and 5 ns, respectively. Thanks to the full synthesizability and the output-capacitor-free design, 16.1-A/mm$^{2}$ current density is achieved, which is the best performance compared to prior state-of-the-art DLDOs. © 1986-2012 IEEE.
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