Asymmetric SOI CMOS Switch With Series and Parallel Resonators to Enhance Isolation
- Authors
- Kwon, Jaehyun; Lee, Jaeyong; Kim, Taehun; Seo, Donghwan; Yoo, Jinho; Cho, Jaeheon; Park, Changkun
- Issue Date
- Apr-2024
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Resonators; Switching circuits; Transistors; Switches; Resonant frequency; ISO; Simulation; Asymmetric; isolation; resonance; single-pole double-throw (SPDT); switch
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.71, no.4, pp 1964 - 1968
- Pages
- 5
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
- Volume
- 71
- Number
- 4
- Start Page
- 1964
- End Page
- 1968
- URI
- https://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/49535
- DOI
- 10.1109/TCSII.2023.3332177
- ISSN
- 1549-7747
1558-3791
- Abstract
- In this brief, we designed an asymmetric single-pole double-throw (SPDT) switch that operates at 1.9 - 2.4 GHz. To improve the isolation in the Rx mode, which is a disadvantage of asymmetric SPDT switches, a series and parallel resonance structure was proposed and analyzed. The proposed series and parallel resonance structure has been applied to the asymmetric SPDT switch. In addition, in order to secure the power handling capability of the switch, all transistors constituting the switch were designed to be in the on-state in the Tx mode. To verify the feasibility of the proposed structure, an asymmetric switch was designed using 130-nm partially depleted SOI CMOS process. The isolations in Rx and Tx modes were measured to be higher than 28.6 dB and 41.3 dB, respectively. The insertion loss was measured to be less than 1.79 dB in the same frequency range. The input 1-dB compression points (IP1dBs) measured at 2.2 GHz were 6.7 dBm and 38.8 dBm in Rx and Tx modes, respectively. The core size of the designed SPDT switch is 0.27 mm2.
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