Large-Area CVD-Grown Sub-2 V ReS2 Transistors and Logic Gates
- Authors
- Dathbun, Ajjiporn; Kim, Youngchan; Kim, Seongchan; Yoo, Youngjae; Kang, Moon Sung; Lee, Changgu; Cho, Jeong Ho
- Issue Date
- May-2017
- Publisher
- AMER CHEMICAL SOC
- Keywords
- ReS2; chemical vapor deposition (CVD); transistor; large area; logic gate
- Citation
- NANO LETTERS, v.17, no.5, pp.2999 - 3005
- Journal Title
- NANO LETTERS
- Volume
- 17
- Number
- 5
- Start Page
- 2999
- End Page
- 3005
- URI
- http://scholarworks.bwise.kr/ssu/handle/2018.sw.ssu/6390
- DOI
- 10.1021/acs.nanolett.7b00315
- ISSN
- 1530-6984
- Abstract
- We demonstrated the fabrication of large-area ReS2 transistors and logic gates composed of a chemical vapor deposition (CVD)-grown multilayer ReS2 semiconductor, channel and graphene electrodes. Single-layer graphene was used as the source/drain and coplanar gate electrodes. Anion gel with an, ultrahigh capacitance effectively,gated the ReS2 channel at a low voltage, below 2 V, through a coplanar gate: The.contact resistance of the ion gel-gated ReS2 transistors with graphene electrodes decreased dramatically compared with the SiO2-devices prepared with Cr electrodes, The resulting transisiors exhibited good device performance, including a maximum electron mobility of 0:9 cm(2)/(V s) and an on/off current ratio exceeding 10(4). NMOS logic devices, such as NOT, NAND, and NOR, gates, were assembled using the resulting transistors as a proof of concept demonstration of the applicability of the devices. to complex logic circuits. The large-area synthesis of ReS2 semiconductors and graphene electrodes and their applications in logic devices open up new opportunities for realizing future flexible electronics based on 2D nanornaterials.
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Collections - College of Engineering > Department of Chemical Engineering > 1. Journal Articles
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