Pipelined phase accumulator using sequential FCW loading scheme for DDFSs
- Authors
- Jung, Y.-H.; Yoo, T.; Cho, S.-J.; Baek, K.-H.
- Issue Date
- Aug-2012
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Citation
- ELECTRONICS LETTERS, v.48, no.17, pp 1044 - 1045
- Pages
- 2
- Journal Title
- ELECTRONICS LETTERS
- Volume
- 48
- Number
- 17
- Start Page
- 1044
- End Page
- 1045
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/15188
- DOI
- 10.1049/el.2012.1342
- ISSN
- 0013-5194
1350-911X
- Abstract
- Presented is a low-power small-area pipelined phase accumulator (PACC) for direct digital frequency synthesisers (DDFSs). To minimise the number of pre-skewing flip-flops, the proposed scheme sequentially loads Frequency Control Word (FCW) input data directly to the corresponding unit accumulators without through series of flip-flops, thus reducing the power consumption as well as the chip area compared to previously reported PACCs. A 24-bit PACC using the proposed scheme is fabricated in a 0.13 mm CMOS process with built-in phase-to-amplitude mapping circuitry and a D/A converter for measurements of the PACC performance. Experimental results show that the proposed architecture reduces power consumption by 21 and 34% compared to CML-based and static CMOS-based conventional PACC designs, respectively.
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Collections - College of ICT Engineering > School of Electrical and Electronics Engineering > 1. Journal Articles
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