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Digitally controlled duty cycle corrector with 1 ps resolution
- Issue Date
- Sep-2007
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- duty cycle corrector; variable delay unit; delay locked loop
- Citation
- IEICE TRANSACTIONS ON ELECTRONICS, v.E90C, no.9, pp 1841 - 1843
- Pages
- 3
- Journal Title
- IEICE TRANSACTIONS ON ELECTRONICS
- Volume
- E90C
- Number
- 9
- Start Page
- 1841
- End Page
- 1843
- ISSN
- 0916-8524
- Abstract
- This letter describes a digitally controlled duty cycle corrector (DCC) with 1 ps resolution. A new half period delay line (HPDL) control scheme using a delay locked loop (DLL) is proposed. The DCC has an output duty error less than 0.5% for 25% input duty error and operates correctly from 200 MHz to 800 MHz in a 0.18 mu m CMOS technology.
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Related Researcher
- Baek, Kwang Hyun
- 창의ICT공과대학 (전자전기공학부)