3D 패키지용 관통 전극 형성에 관한 연구Fabrication of Through-hole Interconnet in Si Wafe for 3D Package
- Authors
- 김대곤; 김종웅; 정재필; 정승부; 신영의; 문정훈; 하상수
- Issue Date
- 2006
- Publisher
- 대한용접접합학회
- Keywords
- Si chip stacking; 3D package; SiP; Through hole; Cu filling; Flip chip
- Citation
- 대한용접접합학회지, v.24, no.2, pp 64 - 70
- Pages
- 7
- Journal Title
- 대한용접접합학회지
- Volume
- 24
- Number
- 2
- Start Page
- 64
- End Page
- 70
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/29173
- ISSN
- 2466-2232
2466-2100
- Abstract
- The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive Ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RF coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.
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Collections - College of Engineering > School of Mechanical Engineering > 1. Journal Articles
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