Experimental Investigation of Physical Mechanism for Asymmetrical Degradation in Amorphous InGaZnO Thin-film Transistors under Simultaneous Gate and Drain Bias Stresses

Abstract

We experimentally investigate the physical mechanism for asymmetrical degradation in amorphous indium-gallium-zinc oxide (a-IGZO) thinfilm transistors (TFTs) under simultaneous gate and drain bias stresses. The transfer curves exhibit an asymmetrical negative shift after the application of gate-to-source (VGS) and drain-to-source (VDS) bias stresses of (VGS = 24 V, VDS = 15.9 V) and (VGS = 22 V, VDS = 20 V), but the asymmetrical degradation is more significant after the bias stress (VGS, VDS) of (22 V, 20 V) nevertheless the vertical electric field at the source is higher under the bias stress (VGS, VDS) of (24 V, 15.9 V) than (22 V, 20 V). By using the modified external load resistance method, we extract the source contact resistance (RS) and the voltage drop at RS (VS, drop) in the fabricated a-IGZO TFT under both bias stresses. A significantly higher RS and VS, drop are extracted under the bias stress (VGS, VDS) of (22 V, 20V) than (24 V, 15.9 V), which implies that the high horizontal electric field across the source contact due to the large voltage drop at the reverse biased Schottky junction is the dominant physical mechanism causing the asymmetrical degradation of a-IGZO TFTs under simultaneous gate and drain bias stresses.