A 1.3-GHz 350-mW Hybrid Direct Digital Frequency Synthesizer in 90-nm CMOS
- Authors
- Yeoh, Hong Chang; Jung, Jae-Hun; Jung, Yun-Hwan; Baek, Kwang-Hyun
- Issue Date
- Sep-2010
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- CMOS direct digital frequency synthesizer (DDFS); digital-to-analog converter (DAC); pipelined accumulator; segmented nonlinear DAC
- Citation
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.45, no.9, pp 1845 - 1855
- Pages
- 11
- Journal Title
- IEEE JOURNAL OF SOLID-STATE CIRCUITS
- Volume
- 45
- Number
- 9
- Start Page
- 1845
- End Page
- 1855
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/48982
- DOI
- 10.1109/JSSC.2010.2056830
- ISSN
- 0018-9200
1558-173X
- Abstract
- This paper presents a low-power direct digital frequency synthesizer (DDFS) based on a hybrid design with a maximum operating frequency of 1.3 GHz. The proposed hybrid design is capable of extending the resolution of traditional nonlinear digital-to-analog converter (DAC)-based DDFS by adding a linear slope component to the approximated sine wave produced from a nonlinear DAC via an additional linear DAC. With an 11-bit combined DAC, the prototype DDFS produces a minimum spurious free dynamic range (SFDR) of 52 dBc from dc up to Nyquist frequency when clocked at 1.3 GHz. This 90-nm CMOS chip occupies 2 mm(2) including bond pads and dissipates 350 mW with a 1.2-V digital supply and 2.5-V analog supply. The FOM of this chip is measured at 1207.9 GHz . 2(ENOB)/W.
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