An FPGA-based parallel accelerator for matrix multiplications in the Newton-Raphson method
- Authors
- Xu, X.; Ziavras, S.G.; Chang, T.-G.
- Issue Date
- Dec-2005
- Publisher
- SPRINGER-VERLAG BERLIN
- Citation
- EMBEDDED AND UBIQUITOUS COMPUTING - EUC 2005, v.3824, pp 458 - 468
- Pages
- 11
- Journal Title
- EMBEDDED AND UBIQUITOUS COMPUTING - EUC 2005
- Volume
- 3824
- Start Page
- 458
- End Page
- 468
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/53235
- DOI
- 10.1007/11596356_47
- ISSN
- 0302-9743
1611-3349
- Abstract
- Power flow analysis plays an important role in power grid configurations, operating management and contingency analysis. The Newton-Raphson (NR) iterative method is often enlisted for solving power flow analysis problems. However, it involves computation-expensive matrix multiplications (MMs). In this paper we propose ail FPGA-based Hierarchical-SIMD (H-SIMD) machine with its codesign of the Hierarchical Instruction Set Architecture (HISA) to speed up MM within each NR iteration. FPGA stands for Field-Programmable Gate Array. HISA is comprised of medium-grain and coarse-grain instructions. The H-SIMD machine also facilitates better mapping of MM onto recent multimillion-gate FPGAs. At each level, any HISA instruction is classified to be of either the communication or computation type. The former are executed by a controller while the latter are issued to lower levels in the hierarchy. Additionally, by using a memory switching scheme and the high-level HISA set to partition applications, the host-FPGA communication overheads can be hidden. Our test results show sustained high performance.
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Collections - College of ICT Engineering > School of Electrical and Electronics Engineering > 1. Journal Articles
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