A 3.2-GHz 178-fs <formula> <tex>_rms</tex> </formula> Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier
- Authors
- Yoon, D.; Jung, D.; Seong, K.; Han, J.; Chung, K.; Kim, J.; Kim, T.T.; Baek, Kwang Hyun
- Issue Date
- Jul-2022
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- Calibration; Clocks; Delay-locked loop (DLL); Delays; injection-locked clock multiplier (ILCM); Jitter; low noise; Phase locked loops; phase-locked loop (PLL); subsampling PLL (SSPLL).; Transfer functions; Voltage-controlled oscillators
- Citation
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.30, no.7, pp 915 - 925
- Pages
- 11
- Journal Title
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Volume
- 30
- Number
- 7
- Start Page
- 915
- End Page
- 925
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/58258
- DOI
- 10.1109/TVLSI.2022.3169636
- ISSN
- 1063-8210
1557-9999
- Abstract
- This article proposes a 3.2-GHz subsampling phase-locked loop (SSPLL)-based injection-locked clock multiplier (ILCM) using a subsampling delay-locked loop (SSDLL). The proposed ILCM achieves a superior noise reduction effect at low offset frequency because of the high feedback gain of SSPLL. Also, SSDLL is proposed for background phase calibration between SSPLL and injection. Since SSPLL and SSDLL use identical SSCP, the power consumption of the frequency and phase calibration is only 1.32 mW. This work is fabricated in a 65-nm CMOS process, and the 10-kHz phase noise is improved by 8.6 dB. The rms jitter from 10 kHz to 30 MHz is 178 fs. The chip-to-chip variations (20 chips) are 17 and 169 fs with/without SSDLL, respectively. The measured results show that FoM₁, FoM₂, and total power consumption are -245.1, -260.1 dB, and 9.85 mW, respectively. IEEE
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