A switch wrapper design for SNA on-chip-network
- Authors
- Chang, J.H.; Yi, J.S.; Kim, J.
- Issue Date
- 2005
- Publisher
- SPRINGER-VERLAG BERLIN
- Citation
- ADVANCES IN COMPUTER SYSTEMS ARCHITECTURE, PROCEEDINGS, v.3740, pp 405 - 414
- Pages
- 10
- Journal Title
- ADVANCES IN COMPUTER SYSTEMS ARCHITECTURE, PROCEEDINGS
- Volume
- 3740
- Start Page
- 405
- End Page
- 414
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/65537
- DOI
- 10.1007/11572961_32
- ISSN
- 0302-9743
1611-3349
- Abstract
- In this paper we present a design of a switch wrapper as a component of SNA (SoC network architecture), which is an efficient on-chip-network compared to a shared bus architecture in a SoC. The SNA uses crossbar routers to provide the increasing demand on communication bandwidth within a single chip. A switch wrapper for SNA is located between a crossbar router and IN connecting them together. It carries out a mode of routing to assist crossbar routers and executes protocol conversions to provide compatibility in IP reuse. A switch wrapper consists of a direct router, two AHB-SNP converters, two interface sockets and a controller module. We implement it in VHDL. Using ModelSim simulation, we confirm the functionality of the switch wrapper. We synthesize it using a Xilinx Virtex2 device to determine resource requirements: The switch wrapper seems to occupy appropriate spaces, about 900 gates, considering that a single SNA crossbar router costs about 20,000 gates.
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Collections - College of ICT Engineering > School of Electrical and Electronics Engineering > 1. Journal Articles
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