Study on Low-jitter and Low-power PLL Architectures for Mobile Audio Systems
- Authors
- Kyung, Y.; Kim, G.S.; Baek, D.
- Issue Date
- Dec-2022
- Publisher
- Institute of Electronics Engineers of Korea
- Keywords
- Clock generator; low jitter; multiplying delay locked loop (MDLL); phase noise; phase-locked loop (PLL); reference-sampling PLL (RSPLL); sub-sampling PLL (SSPLL)
- Citation
- Journal of Semiconductor Technology and Science, v.22, no.6, pp 482 - 492
- Pages
- 11
- Journal Title
- Journal of Semiconductor Technology and Science
- Volume
- 22
- Number
- 6
- Start Page
- 482
- End Page
- 492
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/67352
- DOI
- 10.5573/JSTS.2022.22.6.482
- ISSN
- 1598-1657
2233-4866
- Abstract
- This paper compares four phase-locked loops (PLLs) for mobile audio applications. We compare and analyze PLL structures and discuss the optimized PLL structure in the audio band frequency. A charge-pump-based integer-N PLL (NPLL) is employed as a reference. To improve the jitter performances, multiplying delay-locked loop (MDLL), sub-sampling PLL (SSPLL), and reference-sampling PLL (RSPLL) are employed and analyzed. The frequency range of the PLLs is from 8 MHz to 71.5 MHz. These PLL chips are fabricated using a Samsung 0.13-μm CMOS process. The resulting figures-of-merit for the NPLL, MDLL, SSPLL, and RSPLL are −204.3, −211.07, −220.29, and −213.32 dB, respectively, at 24.576 MHz. The total power consumption from a 1.5-V supply voltage is 1.82, 1.35, 1.43, and 1.64 mW, respectively.
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