Investigation on the RRAM Overshoot Current Suppression with Circuit Simulation

Abstract

In this paper, we have simulated how the overshoot current in the Resistive-switching Random Access Memory (RRAM) cell is generated and whether the integrated transistor can effectively suppress the overshoot current that can cause degradation of cell endurance. We propose a CMOS-friendly 1T1R fabrication process and proceed with circuit simulation using the process parameters. The simulation shows that the internal transistor effectively prevent RRAM overshoot current and be capable of controlling the compliance current.