The positive gate bias annealing method for the suppression of a leakage current in the SPC-Si TFT on a glass substrate
- Authors
- Park, Sang-Geun; Park, Joong-Hyun; Kuk, Seung-Hee; Kang, Dong-Won; Han, Min-Koo
- Issue Date
- 2008
- Publisher
- Materials Research Society
- Citation
- Materials Research Society Symposium Proceedings, v.1066, pp 301 - 306
- Pages
- 6
- Journal Title
- Materials Research Society Symposium Proceedings
- Volume
- 1066
- Start Page
- 301
- End Page
- 306
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/74975
- DOI
- 10.1557/proc-1066-a13-03
- ISSN
- 0272-9172
- Abstract
- We fabricated PMOS SPC-Si TFTs which show better current uniformity than ELA poly-Si TFTs and superior stability compare to a-Si:H TFT on a glass substrate employing alternating magnetic field crystallization. However the leakage current of SPC-Si TFT was rather high for circuit element of AMOLED display due to many grain boundaries which could be electron hole generation centers. We applied off-state bias annealing of VGS=5V, V DS=-20V in order to suppress the leakage current of SPC-Si TFT. When the off-state bias annealing was applied on the SPC-Si TFT, the electron carriers were trapped in the gate insulator by high gate-drain voltage (25V). The trapped electron carriers could reduce the gate-drain field, so that the leakage current of SPC-Si TFT was reduced after off-state bias annealing. We applied AC-bias stress on the gate node of SPC-Si TFT for 20,000 seconds in order to verify that the leakage current of SPC-Si TFT could be remained low at actual AMOLED display circuit after off-state bias annealing. The suppressed leakage current was not altered after AC-bias stress. The off-state bias annealed SPC-Si TFT could be used as pixel element of high quality AMOLED display. © 2008 Materials Research Society.
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