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Investigation of Electrical Performance Degradation in p-AlGaN Gate Heterostructure Field-Effect Transistors Under Various Off-Stress Conditions

Authors
Choi, Hyo-SeungJeong, HunLee, Jeong-HwanKwon, Hyuck-In
Issue Date
Jun-2015
Publisher
AMER SCIENTIFIC PUBLISHERS
Keywords
p-AlGaN Gate HFETs; Off-State Stresses; Electrical Performance Degradation; Charge Trapping
Citation
JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, v.10, no.3, pp 397 - 401
Pages
5
Journal Title
JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS
Volume
10
Number
3
Start Page
397
End Page
401
URI
https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/9537
DOI
10.1166/jno.2015.1757
ISSN
1555-130X
1555-1318
Abstract
We investigate the effects of various off-state stresses on the electrical performance degradation in p-AlGaN gate heterostructure field-effect transistors (HFETs) which are especially devised for the normally-off operation. The devices were stressed under various off-stress conditions and the transfer curves were measured immediately after stresses. When the negative bias stress was applied only to the gate electrode, the drain current (I-D) decreased and the threshold voltage (V-TH) moved to the positive direction. On the other hand, when the devices were stressed at a fixed negative gate voltage with various positive drain voltages, I-D decreased, but V-TH did not move. These degradations are believed to be the results of electron trapping during the off-state stresses, and the observed different phenomena depending on the off-stress conditions may be attributed to the difference of charge trapping locations.
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Kwon, Hyuck In
창의ICT공과대학 (전자전기공학부)
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