Effect of Double Epitaxial Layer on the Latch-Up Immunity in High-Power Devices
- Authors
- Nam, Minwoo; Kwon, Soon Hyeong; Choi, Eunmi; Kim, Areum; Paik, Taejong; Pyo, Sung Gyu
- Issue Date
- Apr-2018
- Publisher
- AMER SCIENTIFIC PUBLISHERS
- Keywords
- Latch-Up Immunity; MOSFET; Epitaxial Layer; P-Substrate
- Citation
- SCIENCE OF ADVANCED MATERIALS, v.10, no.4, pp 476 - 479
- Pages
- 4
- Journal Title
- SCIENCE OF ADVANCED MATERIALS
- Volume
- 10
- Number
- 4
- Start Page
- 476
- End Page
- 479
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/988
- DOI
- 10.1166/sam.2018.3046
- ISSN
- 1947-2935
1947-2943
- Abstract
- We report on the improved latch-up immunity of high-voltage devices fabricated using P-/P++ double-layer epitaxy on a P- substrate without degradation in the electrostatic discharge or electrical parameters for LV, MV, and HV MOSFETs. Backseal polysilicon and backseal oxide were not applied to lower the process cost. The resistivity of P++ epi was fixed at the level of the commercial epi wafer's P++ substrate and that of the P- epi layer at the level of the resistivity of the prime wafer used for this product. Only the thickness of the P- epi layer was split to obtain the optimum condition in order to improve the latch-up immunity without degradation in the electrostatic discharge or other electrical parameters of the transistors. We characterized the boron doping profile uniformity within the wafer after P-/P++ double-layer epi deposition via SIMS.
- Files in This Item
- There are no files associated with this item.
- Appears in
Collections - College of ICT Engineering > School of Integrative Engineering > 1. Journal Articles
![qrcode](https://api.qrserver.com/v1/create-qr-code/?size=55x55&data=https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/988)
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.