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A capacitorless low-dropout regulator with enhanced slew rate and 4.5-quiescent current

Authors
Yeo, JaejinJaved, KhurramLee, JaeseongRoh, JeongjinPark, Jae-Do
Issue Date
Jan-2017
Publisher
SPRINGER
Keywords
Voltage regulator; Low-dropout regulator; High slew rate
Citation
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, v.90, no.1, pp.227 - 235
Indexed
SCIE
SCOPUS
Journal Title
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
Volume
90
Number
1
Start Page
227
End Page
235
URI
https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/10567
DOI
10.1007/s10470-016-0869-z
ISSN
0925-1030
Abstract
In this paper, an output-capacitorless, low-dropout (LDO) voltage regulator with excellent load regulation and fast recovery time was designed using two amplifiers, which provided high gain, high bandwidth (HBW), and high slew rate (HSR). In addition, a one-shot current boosting (OSCB) circuit was added for current control to charge and discharge the parasitic capacitance at the power transistor gate during the load-current transition to improve the response time. The experimental results show that the proposed LDO regulator consumes a quiescent current of only 4.5 and can deliver a maximum load current of 200 mA, while regulating the output voltage at with a 1.2 V power supply. We experimentally verified that for a current transition from 0.1 to 200 mA, the undershoot and overshoot voltages were 260 and , with recovery times of only 0.8 and 0.85 , respectively.
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Roh, Jeong jin
ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)
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