A 60-GHz CMOS Power Amplifier with Combined Adaptive-Bias and Linearizer in 28nm Process

Abstract

This paper presents a 60-GHz CMOS power amplifier with on-chip combined adaptive-bias and linearizer (ABL) in 28-nm process. The proposed ABL adaptively compensates the impedance and gate bias of the proposed PA to expand P1dB with a low phase distortion and high back-off power efficiency. The fabricated PA with ABL with ABL on achieves a peak gain of 21 dB and a 3-dB bandwidth of 55.5 to 69 GHz. The PA with ABL on achieves a peak P1dB 12.5 dBm and PAE1dB of 20.5 % in the overall frequency band. Comparing the results of the PA with ABL off, improvements of 4.2 dB and 11 % are achieved with −2.3 dB insertion loss, respectively. The PA also achieves a peak PSAT of 15 dBm and PAEMax of 27.8%. The PA is implemented in a compact size area of 0.072 mm2 and the dc quiescent power consumption is only 62.4 mW.