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Electrolyte-Gated Vertical Synapse Array based on Van Der Waals Heterostructure for Parallel Computingopen access

Authors
Oh SeyongLee Ju-HeeSeo SeunghwanChoo HyongsukLee DongyoungCho Jeong-IckPark Jin-Hong
Issue Date
Feb-2022
Publisher
Wiley-VCH Verlag
Keywords
hardware artificial neural networks; ion gel; parallel computing; synapse arrays; van der Waals heterostructures; vertical synaptic devices
Citation
Advanced Science, v.9, no.6, pp 1 - 10
Pages
10
Indexed
SCIE
SCOPUS
Journal Title
Advanced Science
Volume
9
Number
6
Start Page
1
End Page
10
URI
https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/112833
DOI
10.1002/advs.202103808
ISSN
2198-3844
Abstract
Recently, three-terminal synaptic devices, which separate read and write terminals, have attracted significant attention because they enable nondestructive read-out and parallel-access for updating synaptic weights. However, owing to their structural features, it is difficult to address the relatively high device density compared with two-terminal synaptic devices. In this study, a vertical synaptic device featuring remotely controllable weight updates via e-field-dependent movement of mobile ions in the ion-gel layer is developed. This synaptic device successfully demonstrates all essential synaptic characteristics, such as excitatory/inhibitory postsynaptic current (E/IPSC), paired-pulse facilitation (PPF), and long-term potentiation/depression (LTP/D) by electrical measurements, and exhibits competitive LTP/D characteristics with a dynamic range (G(max)/G(min)) of 31.3, and asymmetry (AS) of 8.56. The stability of the LTP/D characteristics is also verified through repeated measurements over 50 cycles; the relative standard deviations (RSDs) of G(max)/G(min) and AS are calculated as 1.65% and 0.25%, respectively. These excellent synaptic properties enable a recognition rate of approximate to 99% in the training and inference tasks for acoustic and emotional information patterns. This study is expected to be an important foundation for the realization of future parallel computing networks for energy-efficient and high-speed data processing.
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ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)
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