A Backside-Illuminated Charge-Focusing Silicon SPAD With Enhanced Near-Infrared Sensitivity
- Authors
- Van Sieleghem, Edward; Karve, Gauri; De Munck, Koen; Vinci, Andrea; Cavaco, Celso; Suss, Andreas; Van Hoof, Chris a; Lee, Jiwon
- Issue Date
- Mar-2022
- Publisher
- Institute of Electrical and Electronics Engineers
- Keywords
- Backside illumination (BSI); charge focusing; CMOS integrated circuits; infrared imaging; single-photon avalanche diode (SPAD)
- Citation
- IEEE Transactions on Electron Devices, v.69, no.3, pp 1129 - 1136
- Pages
- 8
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE Transactions on Electron Devices
- Volume
- 69
- Number
- 3
- Start Page
- 1129
- End Page
- 1136
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/112875
- DOI
- 10.1109/TED.2022.3143487
- ISSN
- 0018-9383
1557-9646
- Abstract
- A backside-illuminated (BSI) near-infrared (NIR)-enhanced silicon single-photon avalanche diode (SPAD) for time-of-flight (ToF) light detection and ranging applications is presented. The detector contains a 2- boldsymbol μm -wide multiplication region with a spherically uniform electric field peak enforced by field-line crowding. A charge-focusing electric field extends into a 10- boldsymbol μm -deep absorption volume, whereby electrons generated in all the corners of the device can move efficiently toward the multiplication region. The SPAD is integrated with a customized 130-nm CMOS technology and a dedicated BSI process. The device has a pitch of 15 boldsymbol μm, which has the potential to be scaled down without significant performance loss. Furthermore, the detector achieves a photon detection efficiency (PDE) of 27% at 905 nm, with an excess bias of 3.5 V that is controlled by integrated CMOS electronics, and a timing resolution of 240 ps. By virtue of these features, the device architecture is well-suited for large-format ToF imaging arrays with integrated electronics. © 1963-2012 IEEE.
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