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High-Performance RF Power Amplifier Module Using Optimum Chip-Level Packaging Structure

Authors
Nam, HyosungKim, JihoonJeon, JooyoungJhon, HeesaukKim, Junghyun
Issue Date
Jun-2022
Publisher
Institute of Electrical and Electronics Engineers
Keywords
Chip-level packaging structure; form-factor; GaN HEMT; heat spreader; monolithic microwave integrated circuit (MMIC); output power; power added efficiency (PAE); power amplifier (PA); radio frequency (RF); thermal conductivity; thermal interface materials (TIMs)
Citation
IEEE Transactions on Industrial Electronics, v.69, no.6, pp 5660 - 5668
Pages
9
Indexed
SCIE
SCOPUS
Journal Title
IEEE Transactions on Industrial Electronics
Volume
69
Number
6
Start Page
5660
End Page
5668
URI
https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/112904
DOI
10.1109/TIE.2021.3088328
ISSN
0278-0046
1557-9948
Abstract
This article presents a high-performance radio frequency (RF) power amplifier (PA) module for which an optimum chip-level packaging structure is proposed to reduce the operating temperature of the RF PA monolithic microwave integrated circuit (MMIC). Because the output power (Pout) and the efficiency of an RF PA module are strongly affected by the thermal characteristics of the PA MMIC, various types of heat spreader materials and thermal interface materials have been examined to implement the PA chip-level packaging structure, and the optimum combination is proposed for a performance enhancement of the PA module in this article. In addition, the optimum form-factor of the heat spreader was suggested based on a thermal simulation. To verify the proposed PA chip-level packaging structure, a 10 W 6–18 GHz RF PA MMIC using a commercial 0.25-µm gallium nitride high electron mobility transistor process was designed and implemented for radar applications. The operating temperature of the PA MMIC on the proposed ch p-level packaging structure shows a dramatic reduction of 24.8 °C, and accordingly, the average Pout and average power-added efficiency are enhanced by up to 9.2% and 2.8%, respectively, when compared with a PA module using the conventional chip-level packaging structure.
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ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)
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