SAR ADC with Split-Capacitor Array DAC based on Optimally Tunable Foreground-Calibration

Abstract

Capacitor mismatch caused by imperfect manufacturing process is the serious issue in split-capacitor array digital-to-analog converter (DAC) circuit block of a successive approximation-register analog-to-digital converters, thereby degrading the linearity performance. This paper proposes a foreground calibration technique to calibrate the capacitor mismatch of split-capacitor array DAC by optimally tuning the capacitance of variable capacitor employed in the DAC. The behavioral simulation results using an 8-bit ADC verified that the integral nonlinearity and the differential nonlinearity were enhanced by 0.9LSB and 0.65LSB, respectively.