A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration
- Authors
- Choo, Min-Seong; Kim, Sungwoo; Ko, Han-Gon; Cho, Sung-Yong; Park, Kwanseo; Lee, Jinhyung; Shin, Soyeong; Chi, Hankyu; Jeong, Deog-Kyoon
- Issue Date
- Aug-2021
- Publisher
- Institute of Electrical and Electronics Engineers
- Keywords
- a bang-bang phase detector (BBPD); All-digital; frequency calibration loop (FCL); injection-locked clock multiplication (ILCM); injection-locked oscillator (ILO); path-mismatch calibration loop (PCL); phase domain response (PDR); time-division dual calibration (TDDC)
- Citation
- IEEE Journal of Solid-State Circuits, v.56, no.8, pp 2525 - 2538
- Pages
- 14
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE Journal of Solid-State Circuits
- Volume
- 56
- Number
- 8
- Start Page
- 2525
- End Page
- 2538
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/114114
- DOI
- 10.1109/JSSC.2021.3062554
- ISSN
- 0018-9200
1558-173X
- Abstract
- Although an injection-locked oscillator (ILO) can offer excellent jitter performance on average, its intense phase modification at a given injection rate inevitably degrades spur performance, unless injection timing is carefully controlled. This work investigates a behavioral model of the ILO with digital control of a bang-bang phase detector (BBPD) on a discrete-time domain, a quantitative analysis on the dynamics of the digital injection-locked clock multiplier (ILCM) is provided. Adjusting frequency error between the free-running oscillator and the injection signal is crucial to obtain better spur performance. However, the timing offset caused by the device mismatches hinders it from being correctly compensated. Therefore, we investigate the effect of timing offset (or mismatch) between the replica cells and BBPD and then propose the time-division dual calibration (TDDC) to reduce the discrepancies. In addition, three-stage replica cells are chosen to achieve a robust operation in the phase generating aspect. By removing the residual phase offset using multiple delay cells, the optimum locking point is guaranteed.
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Collections - COLLEGE OF ENGINEERING SCIENCES > SCHOOL OF ELECTRICAL ENGINEERING > 1. Journal Articles
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