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Master-Slave based test cost reduction method for DNN Accelerators
- Issue Date
- Nov-2021
- Publisher
- The Institute of Electronics, Information and Communication Engineers (IEICE)
- Keywords
- Artificial intelligence (AI) accelerators; Design for testability; Fault localization; Scan test; Testability
- Citation
- IEICE Electronics Express, v.18, no.24, pp 1 - 5
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEICE Electronics Express
- Volume
- 18
- Number
- 24
- Start Page
- 1
- End Page
- 5
- ISSN
- 1349-2543
- Abstract
- To achieve reduction in test time of accelerators, broadcasting of test patterns is used for simultaneous testing of processing elements (PEs). However, number of PEs tested simultaneously is limited because of scan shift power constraint. In this letter, a Master-Slave based test pattern application method is proposed that alleviates this scan shift power constraint. PEs are grouped in Subcores, the tester loads the pattern into Master PE of Subcores. From Master, test patterns are loaded into adjacent Slave PEs of Subcore. By limiting scan shift power to one Master PE per Subcore, more PEs are allowed to be tested simultaneously. © 2021 The Institute of Electronics.
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