자가보정을 위한 Averaging-Stage 기반 Split SAR 아날로그-디지털 컨버터

Abstract

Chip makers suffer from performance degradation of a successive-approximation-register (SAR) analog-to-digital converter due to the capacitor mismatch issue caused by imperfect manufacturing process, resulting in serious yield loss. This paper proposes a promising background calibration technique to alleviate performance issues from the capacitor mismatch, by employing a split architecture to average capacitances of two different channels. In the calibration mode, capacitance average process is conducted in the SAR logic along with additional but simple circuits such as variable capacitors, analog demultiplexer and switches. The simulation results showed the significant improvements of total-harmonic-distortion (THD) as 18-dB.