Foreground Digital Calibration for Split-Capacitor DAC in SAR ADC

Abstract

Split-capacitive digital-to-analog converter (CDAC) in successive-approximation-resistor (SAR) analog-to-digital converter (ADC) suffers from the linearity degraded by the capacitor mismatch and by parasitic capacitances from the least-significant-bit (LSB) array. This paper proposes a foreground digital calibration scheme to compensate nonidealities of a split-CDAC. The linearity errors of a split-CDAC are estimated by switching logic based on the proposed digital calibration. Our proposed SAR ADC architecture provides 10.5-bit uncalibrated output to generate 10-bit calibrated output by adding error codes and by multiplying calibration factor. The behavioral simulation results of a 10.5-bit SAR ADC showed the DNL and the INL improved 0.31LSB and 1.27LSB, respectively. SNDR and SFDR were enhanced by 6.2dB and 13dB for each.