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Soft error study on DDR4 SDRAMs using a 480 MeV proton beam
- Authors
- Park, Myungsang; Jeon, Sanghoon; Bak, Geunyong; Lim, Chulseung; Baeg, Sanghyeon; Wen, Shijie; Wong, Richard; Yu, Nick
- Issue Date
- Apr-2017
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- DDR4 SDRAM; logic upset cluster; retention weak bits; single event upset
- Citation
- IEEE International Reliability Physics Symposium Proceedings, pp.1 - 6
- Indexed
- SCIE
SCOPUS
- Start Page
- 1
- End Page
- 6
- ISSN
- 1541-7026
- Abstract
- This paper is a soft error study on logic upset in control logic, using a 480 MeV proton beam on commercial DDR4 SDRAM components from two different manufacturers. Samples with the same density and speed showed a 1.9x difference in logic cross section depending on the manufacturer. Compared to DDR3 SDRAM, DDR4 SDRAM from the same manufacturer showed about 45% SBU cross-section increase, and 17% logic upset decrease. To understand how the storage capacitance of down-scaling DDR technologies affects soft error, soft error bits were compared to retention weak bits. No evidence was found that indicated that retention weak bits were more sensitive to soft error. © 2017 IEEE.
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Related Researcher
- Baeg, Sanghyeon
- ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)