Heterogeneous 3-D Sequential CFETs With Ge (110) Nanosheet p-FETs on Si (100) Bulk n-FETs
- Authors
- Kim, Seong Kwang; Lim, Hyeong-Rak; Jeong, Jaejoong; Lee, Seung Woo; Jeong, Ho Jin; Park, Juhyuk; Kim, Joon Pyo; Jeong, Jaeyong; Kim, Bong Ho; Ahn, Seung-Yeop; Park, Youngkeun; Geum, Dae-Myoung; Kim, Younghyun; Baek, Yongku; Cho, Byung Jin; Kim, Sanghyeon
- Issue Date
- Nov-2023
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- Complementary field-effect-transistors (CFETs); Epitaxial growth; Fabrication; Ge-OI; Germanium; monolithic 3-dimensional (M3D); MOSFETs; Performance evaluation; Silicon; Substrates; Wafer bonding; wafer bonding
- Citation
- IEEE Transactions on Electron Devices, v.71, no.1, pp 1 - 7
- Pages
- 7
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE Transactions on Electron Devices
- Volume
- 71
- Number
- 1
- Start Page
- 1
- End Page
- 7
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/117854
- DOI
- 10.1109/TED.2023.3331669
- ISSN
- 0018-9383
1557-9646
- Abstract
- In this study, we report on the fabrication and characterization of 3-D sequential complementary field-effect-transistors (CFETs) using the direct wafer bonding (DWB) technology and a low-temperature process for monolithic 3-D (M3D) integration. The device features a high-performance top Ge (110)/<inline-formula> <tex-math notation=LaTeX>$\langle$</tex-math> </inline-formula>110<inline-formula> <tex-math notation=LaTeX>$\rangle$</tex-math> </inline-formula> channel on a bottom Si CMOS. To ensure high performance without causing damage to the bottom Si n-FETs, the maximum thermal budget during the fabrication of the top Ge p-FETs was limited to 400 <inline-formula> <tex-math notation=LaTeX>$^{\circ}$</tex-math> </inline-formula>C. We systematically investigated the mobility enhancement of the thin Ge (110) nanosheet (NS) channel p-FETs as a function of channel orientation. Our results demonstrate that the low effective hole mass along the <inline-formula> <tex-math notation=LaTeX>$\langle$</tex-math> </inline-formula>110<inline-formula> <tex-math notation=LaTeX>$\rangle$</tex-math> </inline-formula> direction on Ge (110) wafer provides record-high mobility of 400 cm<inline-formula> <tex-math notation=LaTeX>$^{\text{2}}$</tex-math> </inline-formula>/V<inline-formula> <tex-math notation=LaTeX>$\cdot$</tex-math> </inline-formula>s (corresponding to 760 cm<inline-formula> <tex-math notation=LaTeX>$^{\text{2}}$</tex-math> </inline-formula>/V<inline-formula> <tex-math notation=LaTeX>$\cdot$</tex-math> </inline-formula>s when normalized by footprint) at room temperature, which is the highest reported among the Ge p-FETs with similar channel thicknesses. IEEE
- Files in This Item
-
Go to Link
- Appears in
Collections - COLLEGE OF SCIENCE AND CONVERGENCE TECHNOLOGY > DEPARTMENT OF PHOTONICS AND NANOELECTRONICS > 1. Journal Articles
![qrcode](https://api.qrserver.com/v1/create-qr-code/?size=55x55&data=https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/117854)
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.