An Analysis of 32-Gb/s and Full-Rate Phase Interpolator based Clock and Data Recovery

Abstract

This paper presents a 32-Gb/s full-rate clock and data recovery (CDR) architecture based on a phase interpolator (PI), which incorporates high-speed channel equalization to widen the ppm tolerance or locking range. This work focuses on the receiver-side implementation. Therefore, the feed-forward equalizer (FFE) tap is not utilized, and only the voltage swing level is adjusted at the transmitter side. The channel is modeled using Verilog language with a -10 dB loss at 10 GHz. The overall architecture comprises several components: a continuous-time linear equalizer (CTLE), 1-tap decision feedback equalizer (DFE), 7-bit PI, digital loop filter, and 2x oversampling phase detector. By individually employing the DFE and CTLE, the optimal tap coefficient value for the DFE, which produces the widest eye pattern, and the pole and zero positions of the CTLE are determined. Finally, CTLE and 1-tap DFE ensure optimal vertical 322 mV and timing margin of 25.8 ps. It also relaxes phase modulation to obtain acceptable error of the phase interpolator up to ±15625 ppm. © 2024 IEEE.