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Hardware and Software Co-Simulation Methodology for Processing-in-Memory Bitcell application
- Authors
- Lee, Jae-Gun; Kang, Shin-Uk; Choo, Min-Seong
- Issue Date
- Jan-2024
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- embedded dynamic-random access memory (eDRAM); multilayer perceptron (MLP); neural network; processing in memory (PIM); static-random access memory (SRAM)
- Citation
- 2024 International Conference on Electronics, Information, and Communication (ICEIC), pp 1 - 2
- Pages
- 2
- Indexed
- SCOPUS
- Journal Title
- 2024 International Conference on Electronics, Information, and Communication (ICEIC)
- Start Page
- 1
- End Page
- 2
- ISSN
- 0000-0000
- Abstract
- This paper proposes a reliable design methodology for processing-in-memory (PIM) Macro design. Instead of focusing on neural network training and inferencing in full precision, whether deep neural network (DNN) or convolutional neural network (CNN), we present an efficient and accurate performance evaluation methodology through simulation that considers the characteristics of actual bitcells in use. Additionally, we suggest necessary hardware design constraints to achieve high accuracy. © 2024 IEEE.
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Related Researcher
- Choo, Min Seong
- ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)