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Automatic Tuning of Negative-R Circuit for High-Performance 95-dB DR 5-kHz Bandwidth Continuous-Time Delta-Sigma Modulator

Authors
Shin, HwaseongSong, SeokjaeJeong, HyunjiDuan, QuanzhenRoh, Jeongjin
Issue Date
Apr-2024
Publisher
Institute of Electrical and Electronics Engineers
Keywords
Continuous-time delta-sigma modulator; chopped negative-R; auto-tuning; analog-to-digital converter; duty-cycle resistor
Citation
IEEE Transactions on Circuits and Systems I: Regular Papers, v.71, no.6, pp 1 - 10
Pages
10
Indexed
SCIE
SCOPUS
Journal Title
IEEE Transactions on Circuits and Systems I: Regular Papers
Volume
71
Number
6
Start Page
1
End Page
10
URI
https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/118907
DOI
10.1109/TCSI.2024.3383455
ISSN
1549-8328
1558-0806
Abstract
This paper presents a continuous-time delta-sigma modulator (CTDSM) for applications that require a 5-kHz signal band and high resolution. The number of applications that use negative-R to compensate for the DC-gain, unity gain bandwidth (UGB), and noise of operational amplifiers (op-amps) is increasing. However, due to process-voltage-temperature (PVT) variations, conventional negative-R has limitations in providing ideal compensation. Therefore, this paper presents an auto-tuning (AT) negative-R that can automatically calibrate for PVT variations, overcoming the limitations caused by mismatching issues in conventional negative-R. The proposed single-bit 3rd-order CTDSM applies AT negative-R to the first integrator, resulting in consistent and optimal integrator performance. The designed CTDSM was successfully fabricated in a 28-nm CMOS process and achieved the following measurement results: a peak signal-to-noise ratio (SNR) of 92.41 dB, a peak signal-to-noise and distortion ratio (SNDR) of 90.91 dB, a dynamic range (DR) of 95 dB, total power consumption of 24 mu W (at a supply voltage of 1 V), and a signal bandwidth of 5 kHz.
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ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)
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