3.2-GHz Digital Phase-Locked Loop With Autocorrelation-Based Direct Jitter Correction
- Authors
- Park, Gijin; Yeom, Sunoh; Jang, In-Woo; Lee, Dongjun; Han, Jaeduk; Choo, Min-Seong
- Issue Date
- Apr-2024
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- Adaptive loop gain control (ALGC); autocorrelation; Calculators; Circuits; digital phase-locked loop (DPLL); direct proportional path; Jitter; Phase locked loops; Phase noise; pulse width control (PWC); Quantization (signal); Timing
- Citation
- IEEE Transactions on Circuits and Systems II: Express Briefs, pp 1 - 5
- Pages
- 5
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE Transactions on Circuits and Systems II: Express Briefs
- Start Page
- 1
- End Page
- 5
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/119262
- DOI
- 10.1109/TCSII.2024.3392771
- ISSN
- 1549-7747
1558-3791
- Abstract
- This brief solves the challenge of loop latency in the digital filter of conventional digital phase-locked loops (DPLLs), which hinders timely updates of phase frequency detector error information. To address this latency problem, we introduce a direct path for jitter correction, utilizing a pulse generator with an adaptive pulse width controller (PWC). The impact of PWC-based phase correction is analyzed to optimize the proportional gain in DPLLs. The DPLL, designed with adaptive gain control and realized in 40-nm CMOS technology, significantly enhances its performance metrics. Operating from a 100-MHz reference clock to produce a 3.2-GHz output, the prototype achieves a power consumption of 6.36 mW. Remarkably, the measurements indicate a 25% improvement in integrated jitter, reduced from 1231 to 942 fs, while maintaining comparable reference spur performance relative to conventional DPLL designs.
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