코아의 기능성 래퍼를 IEEE 1500 래퍼로 재사용하기 위한 디자인 기법

Abstract

With the scalability of SoC (System-on-a-Chip), the complexity and the area overhead of test logic are also increasing. Especially the area overhead of design for testable (DFT) logic including IEEE 1500 std. compliant test wrapper has reached approximately 10% of actual design. This paper introduces a design technique to reuse functional wrapper as IEEE 1500 compliant test wrapper which reduces DFT area overhead significantly.