IEEE 802.11a 무선랜을 위한 메모리 분할 구조의 효율적인 인터리버와 디인터리버 설계

Abstract

In this paper, we proposed a efficient interleaver and deinterleaver algorithm for IEEE 802.11a Wireless Lan to transfer Burst Error to Random Error. The key point of proposed interleaving and deinterleaving algorithms is dividual memory architecture. By designing dividual memory, the ineterleaving and deineterleaving processing enable to 48 clk processing for BPSK(BInary Phase SHift Keying), QPSK(Quadrature Phase Shift Keying), 16QAM(Quadrature Amplitude Modulation) modulation condition. Furthermore, by designing parallel architecture of interleaver and deinterleaver, sequence data can be processed. Also, simplified straucture of memory address generator module is achieved. Propesed interleaver and deinterleaver are designed by Samsung 0.35um process technology.