Source optimization for the whole arc slit with minimum optical proximity correction applied to contact hole patterns

Abstract

High NA EUV lithography is essential for advanced semiconductor manufacturing, particularly for DRAM contact hole patterning. One of the primary challenges in high NA systems is the intensity variation between the center and edges of the slit. Additionally, critical dimension differences in the x and y directions are further complicated by anamorphic optics and arc-slit illumination configurations, adding to the overall process complexity in high NA lithography. To address these challenges, we conducted source optimization using a rigorous lithography simulation tool for contact hole patterns, with whole arc-slit configuration. This optimization, considering the full arc-slit effect, successfully reduced intensity variation across the slit. Further refinement in pattern fidelity through threshold level light intensity adjustments improved process margins for both vertical and horizontal patterns. By minimizing the need for optical proximity correction and mask bias, our approach simplifies the pattern transfer process from mask to wafer, enhancing accuracy. Additionally, source optimization combined with precise illumination control significantly improves the process window, particularly when dealing with the arc-slit configuration, facilitating the manufacturability of DRAM patterns in high NA EUV lithography.