Charge sharing based 10T SRAM for low-power
- Authors
- Maroof, Naeem; Sohail, Muhammad; Shin, Hyunchul
- Issue Date
- Mar-2016
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- low-power; 10T; charge sharing; SNM free; single ended
- Citation
- IEICE ELECTRONICS EXPRESS, v.13, no.5, pp.1 - 6
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEICE ELECTRONICS EXPRESS
- Volume
- 13
- Number
- 5
- Start Page
- 1
- End Page
- 6
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/14160
- DOI
- 10.1587/elex.13.20151033
- ISSN
- 1349-2543
- Abstract
- We propose a novel charge sharing bit-line 10T SRAM for differential read and single ended (SE) write. Decoupled read provides high noise margin. Read bit-lines are not charged to full V-DD, and these share charge for read 1 operation. A new write driver is proposed for SE write which charges the write-bit-line conditionally. Virtual power rail is used to suppress bit-line leakages. Compared with 6T SRAM, charge sharing scheme potentially consumes only 25% read and 50% write dynamic power. Thorough comparisons with 6T at 45 nm node show that the proposed 10T design has 2x read static noise margin, 71% reduction in total read and 48% reduction in total write power.
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