An SEU-Tolerant DICE Latch Design With Feedback Transistors

Abstract

This paper presents an SEU-tolerant Dual Interlocked Storage Cell (DICE) latch design with both PMOS and NMOS transistors in the feedback paths. The feedback transistors improve the SEU tolerance by increasing the feedback loop delay during the hold mode. The latch design was implemented in a shift register fashion at a 130-nm bulk CMOS process node. Exposures to heavy-ions exhibited a significantly higher upset LET threshold and lower cross-section compared with the traditional DICE latch design. Performance penalties in terms of write delay, power, and area are non-significant compared to traditional DICE design.