Novel Error Detection Scheme With the Harmonious Use of Parity Codes, Well-Taps, and Interleaving Distance
- Authors
- Jeon, Sang Hoon; Lee, Soonyoung; Baeg, Sanghyeon; Kim, Ilgon; Kim, Gunrae
- Issue Date
- Oct-2014
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Effective interleaving distance; error correction code; interleaving distance; multiple-bit upset; multiple-cell upset; parity code; row depth; single error correction-double error detection; single-event effect; well-tap
- Citation
- IEEE TRANSACTIONS ON NUCLEAR SCIENCE, v.61, no.5, pp.2711 - 2717
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON NUCLEAR SCIENCE
- Volume
- 61
- Number
- 5
- Start Page
- 2711
- End Page
- 2717
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/21588
- DOI
- 10.1109/TNS.2014.2349504
- ISSN
- 0018-9499
- Abstract
- This paper explores the effectiveness of error detection schemes in increasingly multiple-cell upset-dominant technologies, specifically SRAM. A review of interleaving distance, parity codes, and well-taps is conducted to examine each attribute. Then, the paper proposes a novel error detection scheme with the harmonious use of the multiple-cell upset inhibition effects of well-taps, the detectability of parity codes, and an interleaving distance scheme to create an effective error detection scheme that is both flexible and has a high implementation prospect. A row depth model is created to assess the effectiveness of the proposed scheme. The model shows that advanced technologies with greater multiple-cell upset sizes and ratios will experience error detection failures with schemes such as single error correction-double error detection, whereas the proposed scheme remains effective. Experimental data supports the premise that well-taps inhibit multiple-cell upset, as it is found that 1% cross well-taps. The proposed scheme is recognized to be at least three times better against error detection failures than single error correction-double error detection.
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