Experimental Exploitation of Random and Deterministic Data Patterns for Stringent DDR4 I/O Timing Margins

Abstract

In this paper, I/O timing margins are experimentally measured by DQS groups, for a DDR4 RDIMM with 2133 Mbps data rate, to study the margin effects of the special combination and sequence of random and fault-based deterministic data patterns. The most effective 94 data patterns are newly developed after experimentally investigating three test patterns factors, which consist of test algorithms, address directions, and data patterns; the most influential factor was data patterns, which resulted in the average margin reduction of 15.2%. The maximum of 11.8% margin was reduced by the proposed 94 patterns (in comparison to 28-bit PRBS pattern), which was from both selected PRBS and fault-based deterministic data patterns.