Advances in 7.5Gb/s SerDes Modeling using IBISv4.2 (VHDL-AMS and Verilog-AMS)

Abstract

Demonstration of full SerDes channel simulation using detailed vendor models across 5 major ASIC vendors. Correlation of vendor models to hspice, ventor internal matla tool, and to silicon. Demonstraton of vendor model in interopperability in a full SerDes channel simulations(s). Demonstration of VHDL-AMS to Verilog-AMS ineroperability in a SerDes full channel simulation. Model interoperability across several EDA tools. Demonstration of post processing modules (to extrapolate BER) in fully coded AMS.